1. Field of the Invention
The invention relates to a memory circuit comprising memory cells having a resistance memory element, and an evaluation circuit for reading out the memory content of such memory cells. In this case, the resistance memory element can be switched back and forth between a high-resistance state and a low-resistance state by means of electrical pulses.
2. Description of the Related Art
The development of semiconductor memory technology is essentially driven by the requirement for increasing the performance of the semiconductor memories in conjunction with miniaturization of the feature sizes. However, further miniaturization of the semiconductor memory concepts based on storage capacitors is difficult in particular owing to the large quantities of charge that are required for writing to and reading from the storage capacitors and lead to a high current demand. Therefore, thought is increasingly being given to new cell concepts that are distinguished by a significantly lower quantity of charge for the writing and reading operation. Semiconductor memories comprising a resistance memory element are one such promising circuit architecture.
One possible memory concept comprising a resistance memory element is the so-called CBRAM (conductive bridging RAM) cell, in which the resistance memory element comprises an inert cathode electrode, a reactive anode electrode and a porous, highly resistive ionically conductive carrier material in between. Through application of electric fields between the two electrodes, it is possible to produce a conductive path through the carrier material and to clear it away again. Depending on the polarity of the electrical pulses applied between anode electrode and cathode electrode, the reactive anode electrode is dissolved electrochemically and, by means of the metal ions released, an electrically conductive connection between the electrodes is produced or this conductive connection is interrupted again, the metal ions in the carrier material depositing on the anode electrode. CBRAM memory cells can be switched back and forth between a high-resistance state and a low-resistance state, the different resistance values each being assigned a logic state.
In addition to CBRAM memory cells, further resistive memory cell concepts are currently being investigated, such as the phase change memory (PCRAM), for example, in which a metal alloy is heated by means of electrical pulses and switched back and forth between an amorphous phase state and a crystalline phase state in the process. The two states are distinguished by a great difference in their conductivity, which can be utilized for the electrical read-out of the memory cell. A further resistive memory concept is the perovskite memory cell, in which, in a perovskite layer, a structure transition between a high-resistance state and a low-resistance state is produced by means of charge injection. Amorphous silicon continues to be used as carrier material in a resistance memory element of a resistive memory cell; said amorphous silicon, after a forming step, can be switched back and forth between a high-resistance state and a low-resistance state by means of electrical pulses. Consideration is also being given to memory concepts having a polymer layer or an organic storage layer in which states having different conductivities can be produced in the carrier layer on the basis of charge transfer complexes that are influenced by electrical pulses.
During the read-out of a resistance memory element, generally the procedure is such that a capacitor is charged or discharged via the resistance memory element and the electrical potential of the capacitor is then evaluated after a predetermined instant in order thus to determine the logic state of the memory cell comprising the resistance memory element. In this case, the electrical potential of the capacitor or discharged via the resistance memory element is preferably compared with a reference potential and the potential difference is determined.
On account of the relatively small voltage swing which results during the charging or discharging of a capacitor via a memory cell comprising a resistance memory element and which lies in the range of 100 mV to 200 mV e.g. in the case of CBRAM cells, it is necessary, for reliable evaluation of the electrical potential of the capacitor charged or discharged via the resistance element, to set the reference voltage for evaluating the difference between the potentials as exactly as possible between the read voltage for the state “0” and the state “1” of the resistance memory cell. Such precise reference voltage setting can be achieved in principle by means of a voltage regulator. It is advantageous, however, to implement the reference voltage for evaluating the charge state of memory elements with the aid of precisely such memory elements, since this affords the possibility of largely compensating for manufacturing fluctuations or fluctuations in the operating conditions in the memory.
In the case of memory concepts based on the magnetotunnel effect (MRAM) reference voltage generation is known in which two additional memory elements, in the case of which one memory element is set to the state “0” and the other is set to the state “1”, are connected in parallel with one another and the average resistance of these two memory cells is used for generating the reference potential. Such reference voltage generation, as is known from WO 2004/051665 A1, presupposes, however, that the difference between the resistance values of the memory elements for the state “0” and the state “1” amounts to only a few 10%. Averaging of the resistance values for the state “0” and the state “1” generally cannot be used for forming a reference voltage in resistance memory elements, however, since, in resistance memory elements, a large change in resistance usually occurs between the state “0” and the state “1”. This holds true for CBRAM cells, for example, in which the state “0” defined by a carrier material layer without a conductive path has a resistance of 1010Ω, whereas the state “1” defined by a carrier material layer with a conductive path has a resistance of 104Ω. On account of the six orders of magnitude smaller resistance value of the CBRAM cell in the state “1”, upon averaging the resistance values for the state “0” and for the state “1”, the average value would practically correspond to the resistance value for the state “1”. As a consequence, the reference voltage generated with such an average resistance value would then essentially be the read voltage for the state “1” of the CBRAM cell.